common-centroid layout
Imagine you and a friend each plant rows of the same crop across a field that's secretly warmer on one side than the other. If you take the sunny half and your friend takes the shady half, your plants will always outgrow theirs — not because of anything you did, but because the field had a gradient. Now interleave your rows with theirs and arrange them so both your patches are balanced around the exact same center point. The warm-to-cool slant now pours equally into both of you, and on average it cancels. That is the whole idea behind a common-centroid layout: when two devices must match closely — the two halves of a differential pair, the two transistors of a current mirror, a pair of capacitors in a data converter — you split each one into pieces and lay them out so both devices share a common geometric center.
On a silicon wafer the 'warm side' is real: oxide thickness, doping, mechanical stress, and temperature all drift slowly across the die in roughly straight-line gradients. A plain side-by-side pair sees a first-order (linear) difference between them, which shows up as input offset voltage in an amplifier or a current error in a mirror. Because a linear gradient is odd-symmetric about a center point — as much above as below — placing both devices symmetrically around one shared centroid makes that first-order term subtract out, leaving only the much smaller second-order curvature. A common 1-D pattern is the ABBA interdigitated row; in 2-D the classic is the 2x2 cross-quad, A and B on opposite diagonals, so the centroid sits dead center for both.
The catch is that the devices on the outer edge of the array live in a different neighborhood than the ones tucked inside — different etch loading, different stress from what's beside them. So you ring the whole array with dummy devices: extra, electrically inert copies whose only job is to give every 'real' finger identical surroundings. Common-centroid plus dummies is what turns two transistors that are merely drawn the same into two that actually behave the same, which is why analog matching lives or dies on layout, not just schematic.
Why a shared centroid kills the dominant matching error: a straight-line process gradient is symmetric about the center, so its contribution to the two devices is equal and subtracts out.
Common-centroid only cancels linear gradients; it does no good against purely random mismatch, which still shrinks with larger device area (Pelgrom's law) — so designers size devices for random matching AND use common-centroid for systematic gradients.