cache coherence versus memory consistency
/ coherence -> koh-HEER-ens /
These two words sound interchangeable and are constantly confused, but they answer two genuinely different questions, and keeping them separate is one of the most clarifying distinctions in all of concurrency. Coherence is about a SINGLE memory location across all the caches; consistency is about the RELATIVE ordering of accesses to DIFFERENT locations.
Cache coherence is a per-address guarantee provided automatically by the hardware: although each core has its own cache, the coherence protocol ensures that for any one address, all cores agree on a single sequence of values it takes (its modification order) and a write eventually propagates to every cache. You never see a core stuck reading an address's ancient value forever, and two writes to the same address are seen in the same order by everyone. Coherence is invisible plumbing — you basically get it for free and rarely think about it.
Memory consistency is the harder, programmer-visible question: given accesses to MANY different locations, in what orders may they appear to interleave across cores? This is exactly what the memory model and memory_order tags govern, and it is where store buffers, reordering, and fences live. The crucial punchline: coherence does NOT give you consistency. A perfectly coherent machine can still let core A's write to x and write to y become visible to core B in the opposite order, because each address is individually coherent yet their relative ordering is not constrained. So 'the caches are coherent, surely my threads see a consistent view' is a classic false inference — coherence handles one address each; consistency, which you must arrange with atomics and orderings, handles the relationships between them.
Core A: x=1; y=1; Core B: while(y==0){} read x; Coherence guarantees B eventually sees y==1 and x==1 individually, but NOT that x's write is visible before y's — that ordering needs release/acquire, not coherence.
Coherence per-address is not enough; the cross-address ordering you actually rely on is consistency.
Coherence (one address, automatic) does NOT imply consistency (ordering across addresses, your job): 'my caches are coherent' never licenses skipping atomics — and this field covers the distinction, not the coherence-protocol mechanics (the MESI states live in Field j).