a cache side channel
A CPU cache is a small, fast memory that keeps recently used data close, so a second access to the same address is much quicker than the first. That speed difference is helpful — but it is also a leak: by timing how fast an access is, you can tell whether that data was recently touched. A cache side channel turns this 'was it cached?' timing into a window onto what SECRET-dependent memory another piece of code has been accessing.
The two classic techniques make this concrete. In Flush+Reload (which needs shared memory, such as a shared library between attacker and victim): the attacker flushes a specific cache line out of the cache (clflush), lets the victim run, then RELOADS that same line and times it. A fast reload means the victim touched that line (it is cached again); a slow reload means it did not. If the victim's code accesses table[secret], the attacker learns which entry — and hence the secret — by seeing which line came back fast. In Prime+Probe (no sharing needed): the attacker fills a cache set with its own data (prime), lets the victim run, then re-accesses its data and times it (probe); lines that are now slow were EVICTED by the victim, revealing which cache sets the victim used. Either way, a sequence of fast/slow timings, gathered over many runs to beat noise, reconstructs secret-dependent memory accesses such as the indices used in a cryptographic table lookup.
It matters because it leaks across boundaries that look airtight: between processes, between a sandbox and its host, even between virtual machines on the same physical CPU, all without violating any memory permission. It is also the measurement engine underneath Spectre and Meltdown — those attacks coax the CPU into speculatively loading a secret into the cache, then read it out through exactly this Flush+Reload trick. The honest framing: cache side channels are hard to fully close because caching is fundamental to performance; mitigations include constant-time, data-independent memory access patterns in sensitive code, cache partitioning, and not co-locating untrusted tenants on shared hardware — each costing performance.
// Flush+Reload, one probed line: clflush(&probe); // 1. evict probe from cache run_victim(); // 2. victim may access probe if secret bit is set t0 = rdtsc(); x = probe; // 3. reload and time it t1 = rdtsc(); // (t1 - t0) small => victim touched it (cached) => that secret bit was set
A fast reload betrays that the victim accessed the line — one bit of a secret leaked through cache timing.
No memory-permission rule is broken — the leak is pure timing — so it crosses process and VM boundaries; cache side channels are also the read-out mechanism that makes Spectre and Meltdown observable.