cache coherence
Imagine several editors each working from a photocopy of the same page. The page lives in a library (main memory), but to work fast each editor keeps a personal photocopy on their desk (their cache). Now one editor crosses out a sentence on their copy. Everyone else is still reading the old sentence on their copies, and the library's master is also out of date. Whose copy is the truth? Cache coherence is the rule and the machinery that makes sure all the copies agree, so no core ever reads a value that another core has already overwritten.
Here is the precise problem. In a multicore chip, each core has a private cache, and shared data can sit in several caches at once. If core A writes a new value to its cached copy of address X, core B's cached copy of X is now stale — yet B will happily read it and compute on wrong data. A coherent system guarantees two things: a read of X returns the most recent write to X (write propagation), and all cores agree on the order of writes to X (write serialization). It does this by having caches track the state of each line and react when another core touches the same line.
Coherence is automatic and invisible to correctness — software does not ask for it, the hardware just provides it — which is wonderful, but it is not free. Keeping copies in agreement means cores must communicate behind the scenes whenever shared data is written: invalidating or updating other copies, which costs cycles and bandwidth. Two protocol families do this work, snooping and directory-based, and a subtle performance trap called false sharing can make coherence traffic explode even when cores touch logically separate data. Coherence is the silent tax of shared memory.
Core A and core B both cache X = 5. Core A writes X = 6. Without coherence, B still reads X = 5 from its own cache and computes wrong. With coherence, A's write either invalidates B's copy (so B's next read misses and fetches 6) or updates it (so B's copy becomes 6 immediately). Either way, B can never read the stale 5.
Coherence guarantees a read returns the latest write — by invalidating or updating other cores' stale copies whenever shared data changes.
Coherence (do all copies of one address agree on its latest value?) is distinct from the memory consistency model (in what order may writes to different addresses become visible?). A system can be coherent yet still allow surprising orderings.