architectural registers
Architectural registers are the tiny set of named storage slots that instructions work on directly — the processor's workbench. Imagine a workshop with a huge warehouse out back (memory) but only a few slots on the bench right in front of you (registers). You can grab a tool from the bench instantly, but fetching from the warehouse takes a walk. Almost all computing happens on the bench: you bring a few values up close, work on them, and put results back. Registers are by far the fastest storage in the machine.
There are only a handful of them on purpose — RISC-V has 32 integer registers (x0 through x31), MIPS the same. They are named, not addressed: instructions refer to 'register 5', not 'memory location 5'. They are small (one machine word each, e.g. 64 bits) and few because the instruction format must encode a register number in just a few bits, and because making a small storage array fast is far easier than making a big one fast. By convention some registers have special roles: in RISC-V x0 always reads as zero (a free constant), and others are reserved for the stack pointer and return address by the calling convention.
The word 'architectural' is doing careful work here. These are the registers the ISA promises software it can see and use — the visible contract. A high-performance chip may have many more hidden physical registers inside and shuffle values among them (register renaming) to run instructions out of order, but software never sees those; it only ever names the architectural ones. So 'architectural register' means 'the registers in the ISA's menu', as distinct from whatever extra scratch space the implementation secretly keeps.
In RISC-V, register x0 is hardwired to zero. To set a register to a constant 7, you can write 'addi x5, x0, 7' — add 7 to zero. The free zero register saves needing a separate 'load constant' instruction for this common case.
A hardwired-zero register turns 'set to constant' into a plain add — a small but clever ISA choice.
Architectural registers (what software sees) are not the same as physical registers (what the chip actually has). A modern core may have 200+ physical registers mapped onto its 32 architectural names — but that is invisible to your program.