Data converters & PLLs

analog-to-digital converter (ADC)

An analog-to-digital converter is the doorway from the messy continuous world into the clean world of numbers your digital chip can actually compute on. A microphone, a temperature sensor, a radio antenna — they all speak in smoothly varying voltages, an infinite shade of grey between high and low. An ADC listens to that voltage and hands the processor a number. It does this in two moves. First it samples: like a camera snapping frames, it freezes the voltage at evenly spaced instants instead of watching it forever. Then it quantizes: it rounds each frozen value to the nearest rung on a fixed ladder of levels, because a number can only have so many digits. Sampling chops up time; quantizing chops up amplitude.

Two honest costs come with that convenience. You must sample fast enough — at least twice the highest frequency you care about (the Nyquist rule, fs greater than 2*fmax) — or fast wiggles disguise themselves as slow ones, an error called aliasing that no later math can undo. And rounding to the nearest rung throws away the tiny leftover, which acts like a faint hiss called quantization noise. More bits means a finer ladder and a quieter hiss: for an ideal converter the signal-to-noise ratio is about 6.02*N + 1.76 dB, so each extra bit buys you roughly 6 dB of headroom. That single line is why a 16-bit audio ADC sounds so much cleaner than an 8-bit one.

Which architecture you reach for is a trade between speed, resolution, and power. A flash ADC is the sprinter: it compares the input against every ladder rung at once with a bank of comparators, so it converts in a single tick — blisteringly fast, but the comparator count explodes with bits, so it stays low-resolution and power-hungry (think multi-gigahertz radio and oscilloscope front-ends). A SAR (successive-approximation) ADC plays a binary-search guessing game, pinning down one bit per step; it lands in the comfortable middle — moderate speed, 8 to 18 bits, frugal power — which makes it the workhorse of sensors and microcontrollers. A sigma-delta ADC trades speed for accuracy: it samples far faster than needed and cleverly pushes its quantization noise up out of the band of interest (noise shaping), then filters it away, reaching the highest resolutions (up to ~24 bits) for audio and precision instrumentation.

SNR(dB) = 6.02*N + 1.76 (ideal full-scale sine, N-bit quantizer)

Each extra bit of resolution buys about 6 dB more signal-to-noise ratio, so the SNR ceiling tracks the bit count almost linearly.

Datasheet bit count is the easy part — what designers really chase is the effective number of bits (ENOB), the resolution left after real-world noise, jitter, and distortion eat into the ideal, and it is almost always lower than the nominal N.

Also called
ADCA/D converterA-to-D converter模数转换器类比数位转换器